Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al,-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., electrically conductive features) in a dielectric material having a dielectric constant that is less than the dielectric constant of silicon oxide.
The strategy to introduce low k materials (dielectric materials whose dielectric constant is less than the dielectric constant of silicon oxide) into advanced interconnect structures is difficult to implement due to the new materials chemistry of the low k materials that are being introduced. Firstly, low k materials exhibit fundamentally weaker electrical and mechanical properties as compared to silicon oxide. Secondly, the low k dielectric materials are typically susceptible to damage during the various interconnect processing steps. The damaged observed in the low k dielectrics is manifested by an increase in the dielectric constant and an increased moisture uptake, which may result in reduced performance and degraded device reliability.
Prior art interconnect integration schemes are very complex, inefficient, and costly. For example, a via-first LTO (low temperature oxide) integration scheme requires ten layers of films and twenty-one process steps to form a two-layer dual damascene dielectric structure. In other words, 80% of the films are not needed in the final interconnect structure.
Although immensely popular in semiconductor manufacturing, the prior art dual damascene integration schemes, such as the via-first LTO integration scheme, suffer from several drawbacks including: First, it constitutes a significant portion of manufacturing cost of advanced semiconductor chips as many layers, up to twelve layers for the state-of-the-art chips, are required to connect the minuscule transistors within a chip and to the printed circuit board. Second, it is a main yield detractor as the many layers of films required to form interconnect structures generate chances for defect introduction and, thus, degrade manufacturing yields. Third, it is very inefficient and embodies enormous complexity. The current dual damascene integration scheme requires many sacrificial films (80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating. Fourth, the performance gain by introduction of new low k materials is often offset by the material degradation (damage) during processing and the need for high k non-sacrificial materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. Fifth, the prior art complex dual damascene process lengthens manufacturing turn-around time and R&D development cycle. Sixth, the plasma etching process is an expensive and often unreliable process and requires significant up-front capital investment.
In view of the above, there is a need to simplify the formation of interconnects (single damascene and dual damascene) for cost-saving and manufacturing efficiency.